1. Field of the Invention
The invention pertains to a memory circuit including at least one array of flash memory cells organized into independently erasable blocks and a controller, and especially to a memory circuit of this type which is designed to emulate a magnetic disk drive. The invention is a method and apparatus for monitoring the disturb effect on each independently erasable block of memory cells of a memory cell array in such a memory circuit, where the disturb effect causes cells of each such block to lose charge from their floating gates in response to performance of operations (e.g., erase and programming operations) in which high voltage is applied to other blocks of the cell array.
2. Description of Related Art
It is conventional to implement a memory circuit as an integrated circuit including an array of flash memory cells and circuitry for independently erasing selected blocks of the cells. FIG. 1 is a simplified block diagram of such an integrated circuit (flash memory chip 103). Each time one such block is erased (or programmed), the so-called "disturb" effect causes cells of others of the blocks to lose charge from their floating gates (this disturb effect will be described in greater detail below). An integrated flash memory chip such as memory chip 103 of FIG. 1 (or a memory system including such a memory chip) can be modified in accordance with the present invention to account for the disturb effect on each of its independently erasable blocks of memory cells, and optionally also to reduce or eliminate errors in reading or writing data which would otherwise result from the disturb effect.
Memory chip 103 of FIG. 1 includes flash memory array circuit 16 (comprising rows and columns of nonvolatile flash memory cells), I/O pins DQ0-DQ15 (for asserting output data to an external device or receiving input data from an external device), input buffer circuits 122, 122A, and 122B, output buffer circuits 128, 128A, and 128B, address buffer 17 for receiving address bits A0 through A17 from an external device, row decoder circuit (X address decoder) 12, column multiplexer circuit (Y multiplexer) 14, and control unit 29 (also denoted herein as "controller" 29).
Each of the cells (storage locations) of memory array circuit 16 is indexed by a row index (an "X" index determined by decoder circuit 12) and a column index (a "Y" index determined by Y decoder circuit 13 of circuit 14). Each column of cells of memory array 16 comprises "n" memory cells, each cell implemented by a floating-gate N-channel transistor. The drains of all transistors of a column are connected to a bitline, and the gate of each of the transistors is connected to a different wordline, and the sources of the transistors are held at a source potential (which is usually ground potential for the chip during a read or programming operation). Each memory cell is a nonvolatile memory cell since the transistor of each cell has a floating gate capable of semipermanent charge storage. The current drawn by each cell (i.e., by each of the N-channel transistors) depends on the amount of charge stored on the cell's floating gate. Thus, the charge stored on each floating gate determines a data value that is stored "semipermanently" in the corresponding cell. In cases in which each of the N-channel transistors is a flash memory device, the charge stored on the floating gate of each is erasable (and thus the data value stored by each cell is erasable) by appropriately changing the voltage applied to the gate and source (in a well known manner).
The individual memory cells (not depicted) are addressed by eighteen address bits (A0-A17), with nine bits being used by X decoder circuit 12 to select the row of array 16 in which the target cell is located and the remaining nine bits being used by Y decoder circuit 13 (of Y-multiplexer 14) to select the appropriate column of array 16. In response to a nine-bit subset of address bits A0-A17, Y decoder circuit 13 determines a column address which selects one column of cells of array 16. In response to the other nine address bits A0-A17, X decoder circuit 12 determines a row address which selects one cell in the selected column.
In a normal operating mode, chip 103 executes a write operation as follows. Address buffer 17 asserts appropriate ones of address bits A0-A17 to circuit 14 and decoder circuit 12. In response to these address bits, circuit 14 determines a column address (which selects one of the columns of memory cells of array 16), and circuit 12 determines a row address (which selects one cell in the selected column). In response to a write command supplied from controller 29, a signal (indicative of data) present at the output of input buffer 122, 122A, and/or 122B is asserted through circuit 14 to the cell of array 16 determined by the row and column address (e.g., to the drain of such cell). During such write operation, output buffers 128, 128A, and 128B are disabled.
In the normal operating mode, chip 103 executes a read operation as follows. Address buffer 17 asserts appropriate ones of address bits A0-A17 to circuit 14 and address decoder circuit 12. In response to these address bits, circuit 14 asserts a column address to memory array 16 (which selects one of the columns of memory cells), and circuit 12 asserts a row address to memory array 16 (which selects one cell in the selected column). In response to a read command supplied from control unit 29, a current signal indicative of a data value stored in the cell of array 16 (a "data signal") determined by the row and column address is supplied from the drain of the selected cell through the bitline of the selected cell and then through circuit 14 to sense amplifier circuitry 33. This data signal is processed in amplifier circuitry 33, buffered in output buffers 128, 128A, and/or 128B, and finally asserted at pins DQ0-DQ15. During such read operation, input buffers 122, 122A, and 122B are disabled.
Chip 103 also includes a pad which receives a high voltage V.sub.pp from an external device, and a switch 121 connected to this pad. During some steps of a typical erase or program sequence (in which the cells of array 16 are erased or programmed), control unit 29 sends a control signal to switch 121 to cause switch 121 to close and thereby assert the high voltage V.sub.pp to various components of the chip including X decoder 12. Voltage V.sub.pp is higher (typically V.sub.pp =12 volts) than the normal operating mode supply voltage (typically V.sub.cc =5 volts or V.sub.cc =5.5 volts) for the MOS transistors of chip 103.
When reading a selected cell of array 16, if the cell is in an erased state, the cell will conduct a first current which is converted to a first voltage in sense amplifier circuitry 33. If the cell is in a programmed state, it will conduct a second current which is converted to a second voltage in sense amplifier circuitry 33. Sense amplifier circuitry 33 determines the state of the cell (i.e., whether it is programmed or erased corresponding to a binary value of 0 or 1, respectively) by comparing the voltage indicative of the cell state to a reference voltage. The outcome of this comparison is an output which is either high or low (corresponding to a digital value of one or zero) which sense amplifier circuitry 33 sends to output buffers 128 and 128E (and through multiplexer 124 to output buffer 128A). One or more of the output buffers in turn asserts a corresponding data signal to corresponding ones of pins DQ0-DQ15 (from which it can be accessed by an external device).
It is important during a write operation to provide the wordline of the selected cell with the proper voltage and the drain of the selected cell with the appropriate voltage level (the voltage determined by the output of each input buffer, asserted through latch/multiplexer 130 to circuit 14), in order to successfully write data to the cell without damaging the cell.
Internal state machine 120 of control unit 29 of chip 103 controls detailed operations of chip 103 such as the various individual steps necessary for carrying out programming, reading and erasing operations. State machine 120 thus functions to reduce the overhead required of a processor (not depicted) typically used in association with chip 103.
Memory operations, including programming, reading, and erasing can be initiated in various ways. For all operations, the chip enable signal CE must be made active (low). To perform a read operation, write enable signal WE must be made inactive (high). For a write operation, signal WE must be made active (low). In order to reduce the likelihood of accidental modification of data, erase and program operations require receipt of two consecutive commands that are processed by command execution logic unit 124. The program and erase commands are provided by the associated processor to data I/O pins DQ0-DQ7, forwarded to input buffer 122, and then forwarded to the command execution logic unit 124 for processing.
If memory array 16 is to be erased (typically, all or large blocks of cells are erased at the same time), the processor causes the Output Enable OE pin to be inactive (high), and the Chip Enable CE and Write Enable WE pins to be active (low). The processor then issues an 8 bit command 20H (0010 0000) on data I/O pins DQ0-DQ7, typically called an Erase Setup command (each of I/O pins DQ0-DQ7 corresponds to an I/O pad). This is followed by issuance of a second eight bit command D0H (1101 0000), typically called an Erase Confirm command. Two separate commands are used to reduce the possibility of an inadvertent erase operation.
The commands are transferred to data input buffer 122, and the commands are then transferred to command execution logic unit 124 of control unit 29. Logic unit 124 then instructs state machine 120 to perform all the numerous and well known steps for erasing array 16.
Once an erase sequence is completed, state machine 120 updates an 8 bit status register 126, the contents of which are transferred to data output buffer 128A which is connected to data I/O pins DQ0-DQ7 of the memory system. The processor periodically polls the data I/O pins to read the contents of status register 126 in order to determine whether an erase sequence has been completed and whether it has been completed successfully.
During a typical erase operation, it is desired to erase all the cells of array 16 (or an erase block of the cells) so that the threshold voltages are all within a specified voltage range. That range is typically a small positive voltage range such as from +1.5 to +3.0 volts. If the erased cells fall within this range, the cell to be read (the "selected" or "target") cell will produce a cell current in a read operation. The presence of cell current flow indicates that the cell is in an erased state (logic "1") rather than a programmed state (logic "0"). Cell current is produced in a selected erased cell if the voltage applied to the control gate of the cell, by way of the wordline connected to X decoder 12, exceeds the threshold voltage of the erased cell. In addition, cells which are not being read ("deselected" cells) are prevented from producing a cell current even if such cells have been erased to a low threshold voltage state. By way of example, for cells located in the same row as the selected cell, by definition, share the same wordline as the selected cell. However, the drains of the deselected cells will be floating thereby preventing a cell current from being generated. Deselected cells in the same column will not conduct cell current because the wordlines of such deselected cells are typically grounded. Thus, the gate-source voltage of these cells will be insufficient to turn on these deselected cells even if they are in an erased state.
An example of a flash memory array which can be employed as memory array 16 of chip 103 is described in U.S. patent application Ser. No. 08/606,246, entitled "Segmented Non-Volatile Memory Array with Multiple Sources with Improved Word Line Control Circuitry," filed on Feb. 23, 1996 and assigned to the assignee of the present application (Attorney Docket No. MCRN-F4100), the specification of which is incorporated herein by reference.
The present invention is particularly useful as an improvement to flash memory systems of the type designed to emulate magnetic disk drive systems. This type of flash memory system is typically implemented as a card (for insertion into a computer system) with a chip set mounted thereon, where the chip set includes an onboard controller and several memory chips controlled by the controller. Each memory chip implements an array of flash memory cells organized into independently erasable blocks. A conventional flash memory system of this type can be modified in accordance with the invention to enable it to account for the "disturb" effect on each independently erasable block of flash memory cells.
In the past, magnetic hard disk systems have been the dominant storage media for computers and related systems. The low cost and high capacity offered by this technology has made magnetic hard disk systems the mainstay in the computer industry. Because of the dominance of this technology, virtually all computer systems use and support this technology. The support of magnetic disk systems is evident by the software associated with the disk drives. The dominant computer operating system known as "DOS" (Disk Operating System) is essentially a software package used to manage a disk system. DOS has been developed by IBM Corporation, Microsoft Corporation, and Novell as the heart of widely used computer software. The first generation of Microsoft Corporation's "Windows" operating system software was essentially a continuation of the original DOS software with a user friendly shell added for ease of use.
The DOS software was developed to support the physical characteristics of hard drive structures, supporting file structures based on heads, cylinders and sectors. The DOS software stores and retrieves data based on these physical attributes. Magnetic hard disk drives operate by storing polarities on magnetic material. This material is able to be rewritten quickly and as often as desired. These characteristics has allowed DOS to develop a file structure that stores files at a given location which is updated by a rewrite of that location as information is changed. Essentially all locations in DOS are viewed as fixed and do not change over the life of the disk drive being used therewith, and are easily updated by rewrites of the smallest supported block of this structure. A sector (of a magnetic disk drive) is the smallest unit of storage that the DOS operating system will support. In particular, a sector has come to mean 512 bytes of information for DOS and most other operating systems in existence. DOS also uses clusters as a storage unit. Clusters, however, are nothing more than the logical grouping of sectors to form a more efficient way of storing files and tracking them with less overhead.
The development of flash memory integrated circuits has enabled a new technology to offer competition to magnetic hard drives and offer advantages and capabilities that are hard to support by disk drive characteristics and features. The low power, high ruggedness, and small sizes offered by a solid state flash memory system make such a flash memory system attractive and able to compete with a magnetic hard disk drive system. Although a memory implemented with flash memory technology may be more costly than a hard disk drive system, computers and other processing systems are being developed that require (or benefit greatly from) use of flash memory features.
Thus, flash memory systems have been developed that emulate the storage characteristics of hard disk drives. Such a flash memory system is preferably structured to support storage in 512 byte blocks along with additional storage for overhead associated with mass storage, such as ECC (error correction code) bits and/or redundant bits. A key to this development is to make the flash memory array respond to a host processor in a manner that looks like a disk so the operating system can store and retrieve data in a known manner and be easily integrated into a computer system including the host processor.
To make a flash memory easily integratable into a host computer, two basic approaches have been developed. One approach is to configure the flash memory as a storage array, and to load special software into the host to translate conventional operating system (e.g., DOS) commands into flash commands and procedures for assertion to the flash memory. This approach uses the host computing power to act as a controller for the utility that manages the flash memory (rather than including such a controller in the flash memory itself).
Another approach is to make the interface to the flash memory identical to a conventional interface to a conventional magnetic hard disk drive. This approach has been analyzed by the PCMCIA standardization committee, which committee has promulgated a standard for supporting flash memory systems with a hard disk drive protocol. A flash memory card (including one or more flash memory array chips) whose interface meets this standard can be plugged into a host system having a standard DOS operating system with a PCMCIA-ATA (or standard ATA) interface. Such a flash memory card is designed to match the latter standard interfaces, but must include an onboard controller which manages each flash memory array independent of the host system. This approach has several advantages, including the following: there are no special system requirements for the host system (so ease of host system design is assured); no extra memory is required in the host, allowing for better use of the host memory; and the flash memory system runs independently of the host, freeing the host computer to do other tasks while the flash memory is storing or retrieving data from a flash memory array. However, the approach requires a controller onboard the flash memory to implement the equivalent of an operating system behind the disk and PCMCIA interface.
In storing sectors or files of data in a flash memory, several problems exist when trying to emulate a DOS file structure and magnetic disk drive data storage methodology. These problems differ, depending on the structure of the flash memory.
For specificity, consider a flash memory array having the structure shown in FIG. 2. This structure may be suitable for low cost applications of the type commonly implemented using low cost magnetic disk drives. Memory array 16 of FIG. 2 has 544 bytes per row of cells (each byte consisting of eight bits, where each memory cell is capable of storing one bit). Thus, each row of cells is equivalent to a magnetic disk sector (512 bytes of data plus 32 bytes of "overhead").
Memory array 16 of FIG. 2 is partitioned into large "decode" blocks of cells (e.g., eight large decode blocks as shown in FIG. 2) that are physically isolated from one another. This partitioning of blocks allows defects in one decode block (e.g., decode block 16A) to be isolated from the other decode blocks in the array, allows defective decode blocks to be bypassed by a controller, and allows for high usage of die and enhances overall yield of silicon produced (driving down the cost of flash mass storage systems).
Throughout this disclosure, the expression "decode block" is used to denote a block of cells of a memory array which are sufficiently physically isolated from the other cells of the array that the disturb effect on the cells in the decode block (due to high voltage application to the other cells of the array, e.g., during erasing or programming of the other cells) is negligible. In one case, an entire memory array is a single decode block. More typically, a memory array includes two or more decode blocks.
The invention contemplates that each decode block is subdivided into a number of independently erasable blocks (e.g., eight "erase" blocks as shown in FIG. 2), sometimes referred to herein as "erase blocks." In the FIG. 2 example, each erase block (e.g., erase block 16B) consists of rows of flash memory cells, with each row being capable of storing seventeen "packets" of bits, and each packet consisting of 32 bytes (each byte consisting of eight bits). Thus, each row (capable of storing 544 bytes) corresponds to one conventional disk sector (comprising 544 bytes), and each row can store 512 bytes of user data as well as a field of 32 ECC bytes for use in error detection and correction and other bits associated with sector management. In the FIG. 2 example, each erase block corresponds to two "cylinders" of data (in the sense that this expression is used in a conventional magnetic disk drive), with each cylinder consisting of 256K bits of data organized into 64 sectors. Thus, each erase block in the FIG. 2 example consists of 128 sectors of data.
Still with reference to FIG. 2, each erase block (e.g., erase block 16B) can be independently erased in response to signals from the controller. All flash memory cells in each erase block are erased at the same (or substantially the same) time, so that erasure of an erase block amounts to erasure of a large portion of array 16 at a single time. During erasure (or programming) of one erase block, the other erase blocks in the decode block that are not erased (or programmed) are subject to array stresses as the one erase block is erased (or programmed).
As each erase block is programmed and later erased as part of a decode block, the other erase blocks in the decode block are affected by this activity (in the sense that high voltage stresses resulting from the programming and erase operations are seen by the cells comprising the other erase blocks). The effect of an erase (or programming) operation in one portion (e.g., an erase block) of an array on another portion (e.g., another erase block) of the array is known as "disturb." Even where each erase operation produces only a small disturb effect, if this effect is not taken into consideration when building a flash memory (especially one which emulates a disk drive) and if preventive measures are not taken to nullify the accumulated disturb effects of many program and erase operations, the accumulated effects of many program and erase operations will result in failures (upon reading data from the blocks subject to the disturb effect).
In many normal usages of flash memory systems, the entire memory is written (or erased) or entire decode blocks are written (or erased) at one time, which minimizes the disturbs (from each erase block to other erase blocks) which occur. However, in a disk emulation system this is not possible, as the data is very dynamic with small portions (e.g., individual rows) being rewritten many times while other small portions remain unchanged. To accomplish the latter type of data updating, the controller will write data to free locations (e.g., rows) and when the memory is to be updated it will write the new (updated) data to other free rows (not previously written), marking the previously written rows as old (obsolete, and ready to be erased). The system will keep track of these obsolete rows and will erase an entire erase block when it becomes filled or almost filled with obsolete rows. Updated data (to replace data in one row of one erase block) may be placed in another erase block or even another decode block or possibly even a different flash memory chip. The constant rewriting and moving of files will result in erase blocks being constantly programmed and erased. In DOS it is typical for new files to be updated heavily and unused files to be not updated or never changed once generated. This typical use of files will result in portions of memory being updated frequently while other areas will remain stagnant and unchanged. The files and data space being constantly updated pose no problem as they are updated before the surrounding disturbs can cause a problem. The areas of potential failure (in a flash memory system emulating a magnetic disk drive) are the erase blocks within a decode block that are not changing, but are subject to disturbs due to programming and erasures of other erase blocks within the same decode block.
As these disturb conditions exist and are induced on the stored data, the unchanging cells (which store data that is not changed) will tend to lose charge from their floating gates. This charge loss will result in each programmed cell (which stores a data bit indicative of a logical "zero" before occurrence of the disturb effect) gradually moving to a state in which a read operation will indicate (erroneously) that it stores a logical "one" bit. In other words, at some point, this charge loss will result in enough loss that the sense amplifier trip point will no longer see the cell as being programmed and will detect it as an erased cell. Once this has occurred within the memory we will have a data bit failure or several data bit failures.
To better appreciate the manner in which the disturb effect can occur, consider an example in which the following sequence of operations is performed on the eight erase blocks of decode block 16A of FIG. 2 (where the erase blocks of decode block 16A are denoted in the example as Block 0, Block 1, Block 2, Block 3, Block 4, Block 5, Block 6, and Block 7, respectively, in order of increasing distance from the top of FIG. 2): first, all of Blocks 0 through 7 are programmed; then, Block 1 is erased and programmed; then, Block 2 is erased and programmed; then, Block 5 is erased and programmed; then, Block 6 is erased and programmed; then, Block 1 is erased and programmed; then, Block 1 is erased and programmed; then, Block 1 is erased and programmed; and finally, Block 7 is erased and programmed. Following this sequence of operations, Blocks 1 and 7 are least likely to produce a read failure due to the disturb effect (since their cells are the ones most recently updated) and Blocks 0, 3, and 4 are most likely to produce a read failure due to the disturb effect (since their cells are the ones which were exposed to the disturb effect for the longest time following the initial programming of all cells, and are thus the cells likely to have suffered the greatest loss of charge on their floating gates due to the disturb effect). In other words, Blocks 0, 3, and 4 have been subjected to the most disturb without having been updated themselves, and so they are the erase blocks most likely to see a disturb condition which would cause a read failure (an erroneous read of one of the cells) during a subsequent read of all cells of the decode block.
In designing a flash memory system which emulates a magnetic disk drive, it would be ideal to prevent occurrence of the disturb effect by sufficiently isolating small individual blocks of memory cells so no disturbs would occur. However, this ideal solution is impractical if low cost is a criterion for market success, as it is for mass storage systems. However, it often is practical to design a flash memory array that is composed of large decode blocks, where each decode block is effectively isolated from other decode blocks (and thus is not subject to the disturb effect due to programming or erase operations on other decode blocks).
The present invention provides a method and apparatus for accounting for the number of times each erase block (of a decode block) is subjected to the disturb effect due to erasure of other erase blocks in the decode block (without itself undergoing erasure). Thus, the invention allows corrective action to be taken whenever an erase block has been subjected to a predetermined maximum allowable level of the disturb effect. Preferred embodiments of the invention implement such corrective action by performing a refresh operation on each erase block when the decode count for that erase block has reached a predetermined maximum value.